Chiplets divide a complex processor into smaller specialised dies, then use advanced packaging to make them behave like one system.
A chiplet processor divides one complex chip into several smaller pieces, then connects them inside the same package.
Instead of manufacturing every CPU core, memory controller, graphics block and input/output function on one enormous piece of silicon, designers can build specialised dies separately and combine them.
This can reduce manufacturing waste, let different functions use different production processes and make one architecture easier to scale. It also creates a new problem: several chips need to behave like one.
The traditional approach: one monolithic die
A conventional processor is built as a single silicon die. That die may contain:
- computing cores
- cache
- memory controllers
- graphics
- display engines
- PCIe
- and other input/output functions.
A monolithic design has important advantages. Data can move within the die through tightly integrated connections. The system is easier to treat as one physical component. Latency and software behaviour can be more predictable. The disadvantage appears as the die becomes larger. Silicon wafers contain unavoidable defects. A small defect can ruin a much larger piece of valuable silicon. Large dies also fit fewer times onto each wafer.
The bigger and more complex the processor becomes, the harder it is to manufacture efficiently.
Chiplets divide the risk
Imagine a large processor divided into four smaller dies. If a defect affects one small die, the other good dies may still be usable. Smaller pieces also fit onto the wafer more efficiently. This can improve manufacturing yield and reduce the cost of producing a very large total processor. The pieces do not need to be identical. A package might combine:
- high-performance computing dies
- an input/output die
- graphics
- AI acceleration
- cache
- and specialist interfaces.
Each block becomes a building component.
Different jobs can use different manufacturing processes
The most advanced manufacturing process is expensive and not equally useful for every function. High-performance CPU cores can benefit from smaller transistors. Input/output circuits, analogue functions and memory interfaces may not need the same cutting-edge process. Some can work better or more economically on a mature node. Chiplets let designers use the appropriate process for each job.
AMD’s RDNA 3 graphics design, for example, combined a 5nm graphics-compute die with 6nm memory-cache dies. The point was not simply to create more pieces. It was to put different functions on processes suited to them. Intel describes the same wider idea as heterogeneous integration: combining chiplets built for different functions and potentially using different process technologies.
CPUs made chiplets familiar
AMD’s Zen processor families helped bring chiplet design into mainstream desktop and server CPUs. A Ryzen or EPYC package can combine one or more core-complex dies with a separate input/output die. That approach makes it easier to scale the number of cores. A mainstream desktop processor may use one or two compute dies. A server processor can use many more around a central I/O system. The company does not need to design one enormous unique monolithic die for every core count. The same building block can appear across several products.
GPUs are more difficult to divide
Graphics workloads depend on enormous amounts of data moving between computing units, cache and memory. Splitting a GPU can therefore create latency and bandwidth problems. AMD’s RDNA 3 architecture used a central graphics-compute die connected to separate memory-cache dies. The company stated that the interconnect between them could operate at up to 5.3TB/s. That is a vendor peak figure, not real gaming throughput. It illustrates the scale of the connection required.
A chiplet GPU cannot behave like several loosely connected graphics cards. The dies need fast, coherent communication so that software can treat the product as one GPU. This is why chiplet graphics design is not simply “use the CPU method again”.
Packaging becomes part of the architecture
Once the processor is divided, the package connecting it becomes critically important. Traditional package traces may not provide enough bandwidth or energy efficiency. Advanced approaches include:
2.5D integration
Several dies sit beside one another and communicate through an interposer or high-density redistribution layer.
3D stacking
One die sits above another, creating much shorter vertical connections.
Hybrid approaches
Logic, cache and memory can be placed beside and above one another through several packaging technologies. Intel’s Foveros family is an example of advanced 2.5D and 3D integration. AMD also combines chiplets with advanced packaging across CPU, GPU and accelerator products. The package is no longer merely the object protecting the silicon. It determines how the system communicates, receives power and removes heat.
Why not make everything a chiplet?
Chiplets introduce costs of their own.
Communication overhead
Data moving between dies can take more time and energy than movement within one die.
Packaging cost
Advanced interposers, bonding and assembly can be expensive.
Heat density
Stacking dies can make heat removal more difficult.
Testing
Each chiplet and the final package need to be tested. One poor component can still affect the assembled product.
Software and scheduling
The operating system and applications may need to understand differences in latency, cache or core placement.
Product scale
A small inexpensive processor may be cheaper and simpler as one monolithic die.
Chiplets are a design tool, not a universal upgrade.
Are chiplets automatically faster?
No. Chiplets can make a much larger or more specialised processor economically possible. That system may be faster because it contains more cores, cache, memory or acceleration. The chiplet arrangement itself also introduces communication overhead. A well-designed monolithic chip can outperform a poorly designed multi-die system. Performance depends on:
- architecture
- workload
- interconnect
- cache
- memory
- packaging
- software
- and power.
The advantage is flexibility and scale, not free speed.
Why they matter for AI
AI accelerators need enormous computing power, high-bandwidth memory and fast links between several processing blocks. Chiplets allow a designer to combine: computing dies, I/O, cache, high-bandwidth memory and specialist acceleration. AMD’s CDNA architecture uses advanced packaging to combine chiplet technologies and HBM in datacentre accelerators. The wider industry is also moving towards open chiplet-interconnect standards so that dies from different design teams, or eventually different companies, can communicate through common interfaces. That could make processors more modular, although commercial, security and compatibility challenges remain substantial.
What this changes for buyers
Most buyers do not need to choose a processor because it is monolithic or chiplet-based. The useful outcomes are indirect: more cores at a given price, larger caches, better product scaling, more specialised accelerators and greater competition across manufacturing processes. Chiplets can also explain unusual behaviour. A processor may have different latency between groups of cores. A GPU may depend heavily on its cache and interconnect. A stacked-cache design may have different thermal limits from a conventional version. The architecture matters when it changes the real workload, not because “chiplet” appears in the marketing.
The future is likely to be mixed
Some processors will remain monolithic. Others will combine several chiplets. Some will stack cache or memory vertically. Large AI systems may connect many packages so closely that the boundary between chip, module and computer becomes less obvious. The objective is not to create the greatest number of pieces. It is to put each function on the right silicon, manufacture it economically and connect everything quickly enough that the user experiences one system.
Chiplets are changing how processors are built because they allow designers to stop treating one enormous die as the only route to a powerful chip. The smaller pieces are not the breakthrough by themselves. The breakthrough is making them work together. Read why graphics memory is becoming strategically important or explore GPUsed’s enterprise and datacentre hardware.